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The CSG 65CE02 is a 8/16-bit microprocessor developed by Commodore Semiconductor Group in 1988. It is a member of the MOS Technology 6502 family. == Description == The 65CE02 is an improved version of the 6502. It is fabricated using 2 µm CMOS technology, allowing for lower power operation compared to previous NMOS and HMOS versions of the 65xx family. It is housed in a 40-pin DIP that is pin compatible with the 6502. Internally, the pipeline of the 65CE02 was redesigned to reduce the number of cycles required to execute an instruction. The 65CE02 can recover faster from engagement of the SYNC signal, which reduces the minimum instruction execution time from 2 cycles to 1 cycle. These improvements allow the 65CE02 to execute code up to 25% faster than previous 65xx models.〔 Additionally, a third index register (Z) was included, the stack pointer was widened to 16 bits, and the zero page addressing mode was superseded by the more flexible direct page addressing mode.〔 The 65CE02 uses a superset of the GTE 65SC02 instruction set. In addition to the enhancements and bug fixes included in the 65SC02, the 65CE02 includes new instructions for indirect jumps (allows the use of jump tables), 16-bit branches, bit shifting (ASR) and stack relative loads/stores. Several read-modify-write memory instructions (ASL/DEC/INC/PSH/ROR) were enhanced to support 16-bit values. Lastly, instructions supporting the new registers were added. Like the original 6502, the 65CE02 does not include bank switching support. Only 64KB of RAM can natively be accessed. Larger memory configurations require the use of an external MMU. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「CSG 65CE02」の詳細全文を読む スポンサード リンク
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